`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/31 16:15:54
// Design Name: 
// Module Name: mem
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mem(
    clk,reset_n,rd_exe,addr,op_wr_exe,data_2_exe,rd_mem,data_mem,data,op_rd_exe,op_rd_mem,op_b_exe,op_b_mem,
    addr_next_exe,addr_next_mem,zero_exe,zero_mem,sex_imm_b_exe,sex_imm_b_mem,data_fw_1,rd_mem_fw
    );
    input clk,reset_n;
    input [4:0] rd_exe;
    input [31:0] addr;
    input [1:0] op_wr_exe;
    input [31:0] data_2_exe;
    input [1:0] op_rd_exe;
    input [31:0] addr_next_exe;
    input zero_exe,op_b_exe;
    input [31:0] sex_imm_b_exe;
    output reg [4:0] rd_mem;
    output [31:0] data_mem;
    output reg [31:0] data;
    output reg [1:0] op_rd_mem;
    output reg [31:0] addr_next_mem;
    output zero_mem,op_b_mem;
    output [31:0] sex_imm_b_mem;
    output [31:0] data_fw_1;
    output [4:0] rd_mem_fw; 
    
    mem_data mem_data(.clk(clk),.reset_n(reset_n),.addr(addr),.op_wr(op_wr_exe),.data_2_exe(data_2_exe),.data(data_mem));

    assign zero_mem = zero_exe;
    assign op_b_mem = op_b_exe;
    assign sex_imm_b_mem = sex_imm_b_exe;
    assign data_fw_1 = addr;
    assign rd_mem_fw = rd_exe;

    always @(posedge clk) begin
        rd_mem <= rd_exe;
        data <= addr;
        op_rd_mem <= op_rd_exe;
        addr_next_mem <= addr_next_exe;
    end
endmodule
